Bit budget estimation method and device for variable word length encoders

ABSTRACT

The invention is a process and apparatus for estimating a bit budget in a circuit for compressing digital data, especially digitized television signals. Signals represented by N-bit coded samples, are estimated based upon the probability of a bit of given order having a given value (0 or 1) out of M binary words representing M samples of the signal. An entropy calculation is performed on the basis of the probabilities corresponding to the N bits with the sum of all the entropies corresponding to the desired estimate.

The present invention relates to a process for estimating a bit budgetfor encoders with variable word length, as well as to an imagecompression device implementing this process.

In the field of image compression, especially in the field ofhigh-definition television, the images to be compressed are subjected tovarious processing operations (motion estimation, transformation to thefrequency domain, for example by DCT ("Discrete CosineTransformation")), before the data thus obtained are coded fortransmission. To eliminate the redundant data whilst preserving theintegrity of the information, use may be made of coding processes withvariable word length ("Variable length coding" or VLC). These processestake into account the probability with which the data appear among theset of words which are possible for these data. The words which appearoften will then be coded by short binary words and the words whichappear less often will be coded by longer binary words. The consequenceof this will be a reduction in the mean word length, that is to say areduction in the number of bits to be transmitted. The document EP-A-0419 141 describes a variable length coding method.

An example of a device using such variable-length coding is describedbelow.

According to a simplified example of a compression circuit representedin FIG. 1, an RGB video signal is digitized by an analog/digitalconverter 1, feeding an RGB/YUV conversion matrix 2, whose output isconnected to a picture memory 3. An input buffer 4 forms the interfacebetween the picture memory 3 and the motion estimator(s) 5. The resultsof this or these estimation(s) are processed by circuits which are notrepresented in FIG. 1. The signal is furthermore subjected to a discretecosine transformation combinations of non-zero coefficients and oflengths of series of non-zero coefficients are finally coded by avariable-length coding process of known type, for example coding by theHuffman method (circuit 8). A buffer 9 gathers the compressed signalleaving the coder, outputting it as a function of the capacity of thetransmission channel, this channel not being represented in FIG. 1. Aproblem arises when the buffer 9 is filled more quickly than it isemptied. In certain cases, this may lead to an overflow of the bufferand hence to a loss of data. To avoid this problem, a throughputadjustment feedback loop 10 controls the quantizing of the coefficientsof the DCT, and consequently the throughput of data to the buffer 9. Ittherefore seems to be necessary to carry out VLC coding of the databefore being able to ascertain the corresponding bit budget, that is tosay the number of bits required to code the signal or the signal portionin compressed form. This solution is unsatisfactory since it isnecessary to perform a number of purposeless calculations, if the codingis performed in two passes, the first intended for a first estimate ofthe bit budget, the second for the coding per se, possibly with acorrection depending on the results of the first pass. This results in aloss of time and energy, as well as increased complexity of thecircuits.

The purpose of the invention is to avoid these drawbacks.

The purpose of the invention is moreover to allow estimation of the datathroughput leaving the coder, and to do so before the variable wordlength coding.

The subject of the invention is a process for estimating a bit budget ina circuit for compressing digital data, especially digitized televisionsignals, characterized in that, the signals being represented by N-bitsamples, the estimate is based on the probability of a bit of givenorder having a given value out of M binary words representing M samplesof signal, an entropy calculation being performed on the basis of theprobabilities corresponding to the N bits, the sum of all the entropiescorresponding to the desired estimate.

The performance of certain coding methods is known relative to the lowerlimit constituted by the entropy. In the case of the Huffman codingmethod, the mean number of bits required to code a sample of the signalis known to be at most one bit greater than the entropy. Knowing theentropy, or at least an estimate of the entropy, the throughput, or atleast an estimate of the throughput which has to be expected, will beknown even before coding.

In the process according to the invention, the correlation between bitsof like order among the M samples of the signal is taken into accountrather than taking into account directly the correlation between thesamples per se. The estimate thus obtained is necessarily greater thanthe value which would be determined through a conventional entropycalculation. However, the number of comparators and counters requiredfor the calculation is reduced to the number of bits in each sample inthe case of estimation, this representing an appreciable saving ofhardware as compared with the conventional calculation requiring 2^(N)comparators and counters (one comparator and one counter per possiblevalue for the samples).

The subject of the invention is also a device implementing the process.

According to a particular use of the process in accordance with theinvention, estimation of the bit budget serves to forecast thethroughput of the data leaving the coder.

According to a particular use of the invention, estimation of the bitbudget serves to regulate the degree of fill of the video buffer andtherefore to adapt the coding to the throughput of the transmissionchannel.

The process in accordance with the invention can be applied to all kindsof data, be it in the time or frequency domain.

Other advantages of the invention will emerge from the description ofthe non-limiting preferred embodiment represented by the attachedfigures in which:

FIG. 1, already described, represents a partial operating diagram of atelevision signal compression circuit,

FIG. 2 represents the operating diagram of an exemplary layout of theprocess in accordance with the invention,

FIG. 3 represents the operating diagram of a circuit for calculating theentropy corresponding to a bit of order 2^(i), the circuit being used inthe diagram of FIG. 2.

A sample represented by a binary word of length N is of the form:

    .sup.b N-1.sup.b N-2.sup.. . . b.sub.i.sup.. . . b.sub.1.sup.b.sub.0

bi is the bit of order 2^(i) (0≦i≦N-1), each bit being able to take thevalue 0 or 1.

For each bit bi, the number of times Ci that this bit takes the value 1in the M samples is determined. The probability that bi takes the value1 is then pi=Ci/M. The probability that bi takes the value 0 isobviously qi=1-Ci/M.

The entropy, for this bit, is calculated conventionally by using theformula:

    H.sub.i =-p.sub.i Log.sub.2 p.sub.i -q.sub.i Log.sub.2 q.sub.i

this being equivalent to:

    H.sub.i =-(C.sub.i /MLog.sub.2 (C.sub.i /M)-(1-C.sub.i /M) Log.sub.2 (1-C.sub.i /M)

The entropies are next summed for all the bits bi. This sum representsthe desired estimate. By summing over the M samples an estimate of thebit budget is obtained. By dividing by M an estimate is obtained of themean number of bits required to code a word: ##EQU1## bits/word (1)

FIG. 2 shows an operating diagram of a circuit for estimating the numberof bits required to code a signal represented by M N-bit samples. Thecircuit comprises a clock 11 which is synchronous with the frequency ofthe data on a bus 12. The clock 11 delivers a strobe when the data areset up on the bus 12.

Each line of the bus 12 corresponds to a bit bi of a sample representingthe signal and is connected to the input 15i of an L-bit counter 14i.The counters 14i are such that they make it possible to count at leastup to M. L will therefore be chosen such that 2.sup.(L-2)<M≦2.sup.(L-1). The counters moreover possess a clock input 16i, as wellas a zero-reset input 17i. The clock inputs 16i are connected to theclock 11, whereas the zero-reset inputs are connected to the output of acircuit 13.

The circuit 13 includes a counter and a comparator and delivers a signalon its output each time M clock signals have been counted.

The counters 14i are incremented by one unit if, at the time of therising edge of the clock 11 on the input 16i, the input 15i is at 1.

At the start of an estimation phase, all the counters (counters 14i andcounter of the circuit 13) are at zero. Each time

At the start of an estimation phase, all the counters (counters 14i andcounter of the circuit 13) are at zero. Each time a datum correspondingto a digitized signal arises on the bus 12, the clock 11 sends a pulse.The counters 14i are then incremented if their input 15i is high. Thecounter of the circuit 13 counts the number of pulses provided by theclock. If this number exceeds M, the circuit 13 resets its own counterand the counters 14i to zero.

According to a variant embodiment, the state of the counter of thecircuit 13 is delivered to a further circuit, not represented, whichproduces a signal when M words have been counted, so as to advise of thetime at which a correct result is available at the outputs 21 and 22.The ways of implementing such an embodiment are within the scope ofthose skilled in the art.

The output of each counter 14i is connected to the input of acorresponding circuit 18i described later. The circuits 18i each deliverthe entropy corresponding to the bit bi. The entropies are summed by asumming device 19. The result is deducted from the constant term NlogMof equation (1) by the summing device 20. The output 21 or the output 22will be chosen depending on whether an estimate is desired of the totalnumber of bits required to code the M samples or of the mean number ofbits per sample. The output 21 corresponds directly to the output of thesumming device 20, whereas the output 22 corresponds to this outputviewed through a divider by M 23.

FIG. 3 represents an operating diagram corresponding to one of thecircuits 18i. This circuit possesses as input the values of M, as wellas the values of Ci corresponding to the number of times a bit bi was at1 in the M samples.

The circuit principally comprises two logarithmic tables 24 and 25 tothe base 2. The particular feature of these circuits is that theydeliver a zero at output when a zero is present at their input, even ifthe log of zero is normally not defined.

The input of the table 24 receives the term M-Ci, whereas the table 25receives the term Ci. The outputs of the tables each go to a multiplierwhich moreover receives M-Ci and Ci respectively. The outputs from thetwo multipliers are next added up to provide the output from the circuit18i.

According to a variant embodiment, a single logarithm memory is used forall the circuits 18i, a microprocessor or the like being employed toprovide the values from this memory.

According to a variant embodiment, the circuit 13 includes a zero-resetwhich makes it possible to choose precisely from which sample it isdesired to begin estimation, by applying a signal to this input at therequisite time.

The estimate obtained can next be used by the other circuits of thecompression device, especially to regulate the degree of fill of thecompressed-data buffer or to adapt the quantizing of the coefficients.The interaction of the estimation device according to the invention withthe overall device in which it will be installed as well as theregulation per se will be carried out according to one of the layoutsknown to those skilled in the relevant art.

According to a particular embodiment, estimation of the bit budget isperformed in a first pass of the coder, the corresponding result nextbeing used to adapt the quantizing of the coefficients during a secondpass in order to obtain the desired bit rate, the second passterminating with the actual VLC coding, whilst the first pass terminateswith estimation of the bit budget according to the process in accordancewith the invention.

According to a particular embodiment, estimation by the process inaccordance with the invention is obtained after the data have beensubmitted to a Walsh-Hadamard transformation rather than a DCTtransformation. The Walsh-Hadamard transform is simpler to implementthan the DCT transform, requiring only additions and subtractions andnot multiplications. It will also be possible to use the estimateobtained by virtue of the process in accordance with the invention aftera Walsh-Hadamard transformation so as to adapt the quantizing ofcoefficients obtained by DCT.

Implementations of the process other than that given in the exampleabove are of course possible. It will, in particular, be possible toimplement certain steps by means of a microprocessor.

The bit budget estimating process can obviously be used in otherapplications embracing variable-length coders.

I claim:
 1. A process for estimating a bit budget in a circuit forcompressing digital data, which data is represented by N-bit codedsamples, said process comprising:providing the probabilities ofrespective bits of given order having a given value (0 or 1) out of Mbinary words representing M samples of the signal; and performing anentropy calculation on the basis of said probabilities corresponding tothe desired estimate.
 2. A process according to claim 1, wherein thenumber of times Ci(O≦i≦N-1) that a bit of given order possesses thegiven value is determined out of the M samples of the signal, and fromthis entropy Hi of this bit is deduced.
 3. A process according to claim2, wherein when the M binary words have been processed, the entropies Hiare summed to obtain the desired estimate of the bit budget.
 4. Theprocess set forth in claim 1 wherein said bit budget estimatecorresponds to an estimate of a volume of compressed informationexpected to be produced from variable length coding said digital data.5. A process for estimating a bit budget in a circuit for compressingdigital data, which data is represented by N-bit coded samples, saidprocess comprising:providing the probabilities of respective bits ofgiven order having a given value (0 or 1) out of M binary wordsrepresenting M samples of the signal; performing an entropy calculationon the basis of said probabilities corresponding to the desiredestimate; and wherein the estimate of the mean number of bits requiredto code a word is: ##EQU2## where N is the number of bits per sample, Mis the number of samples and C_(i) is the probability of the bit rank Ibeing equal to a given value.
 6. A process for estimating a bit budgetin a circuit for compressing digital data, which data is represented byN-bit coded samples, said process comprising:providing the probabilitiesof respective bits of given order having a given value (0 or 1) out of Mbinary words representing M samples of the signal; counting the numberof times bit of respective orders exhibit said given value in a sequenceof M samples to form N sums; performing an entropy calculation for eachof said N sums to form N entropy values; and combining the N entropyvalues.